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| CrimzonTM ZLR32300 Z8 Low-Voltage ROM MCU with Infrared Timers Product Specification PS022607-1205 ZiLOG Worldwide Headquarters * 532 Race Street * San Jose, CA 95126-3432 Telephone: 408.558.8500 * Fax: 408.558.8300 * www.ZiLOG.com This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact: ZiLOG Worldwide Headquarters 532 Race Street San Jose, CA 95126-3432 Telephone: 408.558.8500 Fax: 408.558.8300 www.zilog.com ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. Document Disclaimer (c)2005 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Devices sold by ZiLOG, Inc. are covered by warranty and limitation of liability provisions appearing in the ZiLOG, Inc. Terms and Conditions of Sale. ZiLOG, Inc. makes no warranty of merchantability or fitness for any purpose. Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights. Disclaimer PS022607-1205 CrimzonTM ZLR32300 Product Specification iii Revision History Each instance in Table 1 reflects a change to this document from its previous revision. To see more detail, click the appropriate link in the table. Table 1. Revision History of this Document Revision Level 03 Page # 1, 2, 11, 12 All 16, 25 Date January 2005 Description Added characterization data, modified Table 8. Removed Preliminary designation April 2005 04 May 2005 05 August 2005 06 Clarified functioning of Port 1 in 20 and 28-packaging. Closes CR5842. Updated Ordering Information on page 85. Removed the 40-pin package. Added caution to Input/Output Ports on page 14. Updated Ordering Information on page 85. Updated section clock and Input/ output port December 07 2005 50, 14 PS022607-1205 Revision History CrimzonTM ZLR32300 Product Specification iv Table of Contents Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii Development Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XTAL1 Crystal 1 (Time-Based Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XTAL2 Crystal 2 (Time-Based Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESET (Input, Active Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Expanded Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Counter/Timer Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop-Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watch-Dog Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Voltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 14 14 22 22 22 22 23 27 28 29 37 47 50 51 52 53 59 62 Expanded Register File Control Registers (0D) . . . . . . . . . . . . . . . . . . . . . . . . 63 Expanded Register File Control Registers (0F) . . . . . . . . . . . . . . . . . . . . . . . . . 68 Standard Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 PS022607-1205 Table of Contents CrimzonTM ZLR32300 Product Specification v Part Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 PS022607-1205 Table of Contents CrimzonTM ZLR32300 Product Specification vi List of Figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Counter/Timers Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 20-Pin PDIP/SOIC/SSOP Pin Configuration . . . . . . . . . . . . . . . . . . . 5 28-Pin PDIP/SOIC/SSOP Pin Configuration . . . . . . . . . . . . . . . . . . . 6 48-Pin SSOP Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Test Load Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 AC Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Port 0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Port 1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Port 2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Port 3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Port 3 Counter/Timer Output Configuration . . . . . . . . . . . . . . . . . . . 21 Program Memory Map (32K ROM) . . . . . . . . . . . . . . . . . . . . . . . . . 23 Expanded Register File Architecture . . . . . . . . . . . . . . . . . . . . . . . . 25 Register Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Register Pointer--Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Glitch Filter Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Transmit Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8-Bit Counter/Timer Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 T8_OUT in Single-Pass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 T8_OUT in Modulo-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Demodulation Mode Count Capture Flowchart . . . . . . . . . . . . . . . . 41 Demodulation Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 16-Bit Counter/Timer Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 T16_OUT in Single-Pass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 T16_OUT in Modulo-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Ping-Pong Mode Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Output Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Port Configuration Register (PCON) (Write Only) . . . . . . . . . . . . . . 52 STOP Mode Recovery Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SCLK Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 STOP Mode Recovery Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 PS022607-1205 List of Figures CrimzonTM ZLR32300 Product Specification vii Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. STOP Mode Recovery Register 2 ((0F)DH:D2-D4, D6 Write Only) 58 WATCH-DOG TIMER Mode Register (Write Only) . . . . . . . . . . . . . 59 Resets and WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 TC8 Control Register ((0D)O0H: Read/Write Except Where Noted) 64 T8 and T16 Common Control Functions ((0D)01H: Read/Write) . . . 65 T16 Control Register ((0D) 2H: Read/Write Except Where Noted) . 66 T8/T16 Control Register (0D)03H: Read/Write (Except Where Noted) .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Voltage Detection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Port Configuration Register (PCON)(0F)00H: Write Only) . . . . . . . 69 STOP mode Recovery Register ((0F)0BH: D6-D0=Write Only, D7=Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 STOP mode Recovery Register 2 ((0F)0DH:D2-D4, D6 Write Only) . .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Watch-Dog Timer Register ((0F) 0FH: Write Only) . . . . . . . . . . . . . 72 Port 2 Mode Register (F6H: Write Only) . . . . . . . . . . . . . . . . . . . . . 72 Port 3 Mode Register (F7H: Write Only) . . . . . . . . . . . . . . . . . . . . . 73 Port 0 and 1 Mode Register (F8H: Write Only) . . . . . . . . . . . . . . . . 74 Interrupt Priority Register (F9H: Write Only) . . . . . . . . . . . . . . . . . . 75 Interrupt Request Register (FAH: Read/Write) . . . . . . . . . . . . . . . . 76 Interrupt Mask Register (FBH: Read/Write) . . . . . . . . . . . . . . . . . . . 76 Flag Register (FCH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Register Pointer (FDH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . 77 Stack Pointer High (FEH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . 78 Stack Pointer Low (FFH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . 78 20-Pin PDIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 20-Pin SOIC Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 20-Pin SSOP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 28-Pin SOIC Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 28-Pin PDIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 28-Pin SSOP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 48-Pin SSOP Package Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Part Number Description Example . . . . . . . . . . . . . . . . . . . . . . . . . 86 PS022607-1205 List of Figures CrimzonTM ZLR32300 Product Specification viii List of Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Revision History of this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . iii Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 20-Pin PDIP/SOIC/SSOP Pin Identification . . . . . . . . . . . . . . . . . . . . 5 28-Pin PDIP/SOIC/SSOP Pin Identification . . . . . . . . . . . . . . . . . . . . 6 48- Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 LR32300 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Port 3 Pin Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 CTR0(D)00H Counter/Timer8 Control Register . . . . . . . . . . . . . . . . 30 CTR1(0D)01H T8 and T16 Common Functions . . . . . . . . . . . . . . . 32 CTR2(D)02H: Counter/Timer16 Control Register . . . . . . . . . . . . . . 35 CTR3 (D)03H: T8/T16 Control Register . . . . . . . . . . . . . . . . . . . . . 36 Interrupt Types, Sources, and Vectors . . . . . . . . . . . . . . . . . . . . . . 49 IRQ Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SMR2(F)0Dh:STOP mode Recovery Register 2* . . . . . . . . . . . . . . 55 STOP Mode Recovery Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Watch-Dog Timer Time Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 ROM Selectable Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 PS022607-1205 List of Tables CrimzonTM ZLR32300 Product Specification 1 Development Features Table 2 lists the features of ZiLOG(R)'s CrimzonTM ZLR32300 family members. Table 2. Features Device CrimzonTM ROM (KB) ZLR32300 4, 8, 16, 24, 32 RAM* (Bytes) I/O Lines Voltage Range 237 32, 24 or 16 2.0V-3.6V Note: *General purpose * * Low power consumption-5 mW (typical) Three standby modes: - STOP--1.4A (typical) - HALT--0.5mA (typical) - Low voltage Special architecture to automate both generation and reception of complex pulses or signals: - One programmable 8-bit counter/timer with two capture registers and two load registers - One programmable 16-bit counter/timer with one 16-bit capture register pair and one 16-bit load register pair - Programmable input glitch filter for pulse reception Six priority interrupts - Three external - Two assigned to counter/timers - One low-voltage detection interrupt Low voltage detection and high voltage detection flags Programmable Watch-Dog Timer/Power-On Reset (WDT/POR) circuits Two independent comparators with programmable interrupt polarity Mask selectable pull-up transistors on ports 0, 1, 2, 3 ROM options - Port 0: 0-3 pull-up transistors - Port 0: 4-7 pull-up transistors - Port 1: 0-3 pull-up transistors - Port 1: 4-7 pull-up transistors - Port 2: 0-7 pull-up transistors * * * * * * * PS022607-1205 Development Features CrimzonTM ZLR32300 Product Specification 2 - - Port 3: 0-3 pull-up transistors WDT enabled at POR General Description The CrimzonTM ZLR32300 is an ROM-based member of the MCU family of infrared microcontrollers. With 237B of general-purpose RAM and 4KB to 32KB of ROM, ZiLOG(R)'s CMOS microcontrollers offer fast-executing, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, automated pulse generation/reception, and internal key-scan pull-up transistors. The CrimzonTM ZLR32300 architecture (Figure 1) is based on ZiLOG's 8-bit microcontroller core with an Expanded Register File allowing access to registermapped peripherals, input/output (I/O) circuits, and powerful counter/timer circuitry. The Z8(R) offers a flexible I/O scheme, an efficient register and address space structure, and a number of ancillary features that are useful in many consumer, automotive, computer peripheral, and battery-operated hand-held applications. There are three basic address spaces available to support a wide range of configurations: Program Memory, Register File and Expanded Register File. The register file is composed of 256 Bytes (B) of RAM. It includes 4 I/O port registers, 16 control and status registers, and 236 general-purpose registers. The Expanded Register File consists of two additional register groups (F and D). To unburden the program from coping with such real-time problems as generating complex waveforms or receiving and demodulating complex waveform/pulses, the CrimzonTM ZLR32300 offers a new intelligent counter/timer architecture with 8-bit and 16-bit counter/timers (see Figure 2). Also included are a large number of user-selectable modes and two on-board comparators to process analog signals with separate reference voltages. Note: All signals with an overline, " ", are active Low. For example, B/W, in which WORD is active Low, and B/W, in which BYTE is active Low. Power connections use the conventional descriptions listed in Table 3. Table 3. Power Connections Connection Power Ground Circuit VCC GND Device VDD VSS PS022607-1205 General Description CrimzonTM ZLR32300 Product Specification 3 P00 P01 P02 P03 I/O Nibble Programmable P04 P05 P06 P07 4 Register File 256 x 8-Bit Port 0 4 Register Bus Internal Address Bus ROM Up to 32K x 8 P10 P11 P12 P13 P14 P15 P16 P17 Internal Data Bus 8 Port 1 Expanded Register File Expanded Register Bus Port 3 Pref1/P30 P31 P32 P33 P34 P35 P36 P37 Z8(R) Core Z8(R) Core I/O Byte Programmable XTAL Machine Timing & Instruction Control RESET I/O Bit Programmable P20 P21 P22 P23 P24 P25 P26 P27 Port 2 Power VDD VSS Watch-Dog Timer Counter/Timer 8 8-Bit Counter/Timer 16 16-Bit Power-On Reset Low Voltage Detection High Voltage Detection Note: Refer to the specific package for available pins. Figure 1. Functional Block Diagram PS022607-1205 General Description CrimzonTM ZLR32300 Product Specification 4 HI16 8 LO16 8 16-Bit T16 Timer 16 1248 8 SCLK Clock Divider TC16H 16 8 TC16L And/OR Logic HI8 8 LO8 8 Timer 8/16 Input Glitch Filter Edge Detect Circuit 8-Bit T8 8 TC8H 8 TC8L Timer 8 Figure 2. Counter/Timers Diagram Pin Description The pin configuration for the 20-pin PDIP/SOIC/SSOP is illustrated in Figure 3 and described in Table 4. The pin configuration for the 28-pin DIP/SOIC/SSOP are depicted in Figure 4 and described in Table 5. The pin configurations for the 48-pin SSOC versions are illustrated in Figure 5 and described in Table 6. PS022607-1205 Pin Description CrimzonTM ZLR32300 Product Specification 5 P25 P26 P27 P07 VDD XTAL2 XTAL1 P31 P32 P33 1 2 3 4 5 6 7 8 9 10 20-Pin PDIP SOIC SSOP 20 19 18 17 16 15 14 13 12 11 P24 P23 P22 P21 P20 VSS P01 P00/Pref1/P30 P36 P34 Figure 3. 20-Pin PDIP/SOIC/SSOP Pin Configuration Table 4. 20-Pin PDIP/SOIC/SSOP Pin Identification Pin # 1-3 4 5 6 7 8-10 11,12 13 14 15 16-20 Symbol P25-P27 P07 VDD XTAL2 XTAL1 P31-P33 P34, P36 Function Port 2, Bits 5,6,7 Port 0, Bit 7 Power Supply Crystal Oscillator Clock Crystal Oscillator Clock Port 3, Bits 1,2,3 Port 3, Bits 4,6 Output Input Input Output Direction Input/Output Input/Output P00/Pref1/P30 Port 0, Bit 0/Analog reference input Input/Output for P00 Port 3 Bit 0 Input for Pref1/P30 P01 VSS P20-P24 Port 0, Bit 1 Ground Port 2, Bits 0,1,2,3,4 Input/Output Input/Output PS022607-1205 Pin Description CrimzonTM ZLR32300 Product Specification 6 P25 P26 P27 P04 P05 P06 P07 VDD XTAL2 XTAL1 P31 P32 P33 P34 1 28 28-Pin PDIP SOIC SSOP 14 15 P24 P23 P22 P21 P20 P03 VSS P02 P01 P00 Pref1/P30 P36 P37 P35 Figure 4. 28-Pin PDIP/SOIC/SSOP Pin Configuration Table 5. 28-Pin PDIP/SOIC/SSOP Pin Identification Pin 1-3 4-7 8 9 10 11-13 14 15 16 17 18 19-21 22 23 24-28 Symbol P25-P27 P04-P07 VDD XTAL2 XTAL1 P31-P33 P34 P35 P37 P36 Pref1/P30 Port 3 Bit 0 P00-P02 VSS P03 P20-P24 Direction Input/Output Input/Output Output Input Input Output Output Output Output Input Input/Output Input/Output Input/Output Description Port 2, Bits 5,6,7 Port 0, Bits 4,5,6,7 Power supply Crystal, oscillator clock Crystal, oscillator clock Port 3, Bits 1,2,3 Port 3, Bit 4 Port 3, Bit 5 Port 3, Bit 7 Port 3, Bit 6 Analog ref input; connect to VCC if not used Input for Pref1/P30 Port 0, Bits 0,1,2 Ground Port 0, Bit 3 Port 2, Bits 0-4 PS022607-1205 Pin Description CrimzonTM ZLR32300 Product Specification 7 NC P25 P26 P27 P04 N/C P05 P06 P14 P15 P07 VDD VDD N/C P16 P17 XTAL2 XTAL1 P31 P32 P33 P34 NC VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48-Pin SSOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC P24 P23 P22 P21 P20 P03 P13 P12 VSS VSS N/C P02 P11 P10 P01 P00 N/C PREF1/P30 P36 P37 P35 RESET Figure 5. 48-Pin SSOP Pin Configuration Table 6. 48- Pin Configuration 48-Pin SSOP # 31 32 35 41 5 7 8 11 33 34 39 Symbol P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 PS022607-1205 Pin Description CrimzonTM ZLR32300 Product Specification 8 Table 6. 48- Pin Configuration 48-Pin SSOP # 40 9 10 15 16 42 43 44 45 46 2 3 4 19 20 21 22 26 28 27 23 47 1 25 18 17 12, 13 24, 37, 38 29 48 6 14 30 36 Symbol P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P31 P32 P33 P34 P35 P36 P37 NC NC NC RESET XTAL1 XTAL2 VDD VSS Pref1/P30 NC NC NC NC NC PS022607-1205 Pin Description CrimzonTM ZLR32300 Product Specification 9 Absolute Maximum Ratings Stresses greater than those listed in Table 8 might cause permanent damage to the device. This rating is a stress rating only. Functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period might affect device reliability. Table 7. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage temperature Voltage on any pin with respect to VSS Voltage on VDD pin with respect to VSS Maximum current on input and/or inactive output pin Maximum output current from active output pin Maximum current into VDD or out of VSS Notes: 1. This voltage applies to all pins except the following: VDD and RESET. Minimum Maximum Units 0 -65 -0.3 -0.3 -5 -25 +70 +150 +4.0 +3.6 +5 +25 75 C C V V A mA mA Notes 1 Standard Test Conditions The characteristics listed in this product specification apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (see Figure 6). From Output Under Test 150pF Figure 6. Test Load Diagram PS022607-1205 Absolute Maximum Ratings CrimzonTM ZLR32300 Product Specification 10 Capacitance Table 8 lists the capacitances. Table 8. Capacitance Parameter Input capacitance Output capacitance I/O capacitance Maximum 12pF 12pF 12pF Note: TA = 25 C, VCC = GND = 0 V, f = 1.0 MHz, unmeasured pins returned to GND DC Characteristics Table 9. LR32300 DC Characteristics Parameter Supply Voltage Clock Input High Voltage Clock Input Low VCL Voltage Input High Voltage VIH Input Low Voltage VIL Output High Voltage VOH1 VOH2 Output High Voltage (P36, P37, P00, P01) Output Low Voltage VOL1 Output Low Voltage VOL2 (P00, P01, P36, P37) VOFFSET Comparator Input Offset Voltage Comparator VREF Reference Voltage Input Leakage IIL RPU IOL ICC Pull-Up Resistance Output Leakage Supply Current 2.0-3.6 2.0 3.6 Symbol VCC VCH VCC 2.0-3.6 2.0-3.6 2.0-3.6 2.0-3.6 2.0-3.6 2.0-3.6 2.0-3.6 2.0-3.6 2.0-3.6 2.0-3.6 0 TA= 0C to +70C Min Typ(7) Max Units Conditions 2.0 3.6 V See Note 5 0.8VCC VCC+0.3 V Driven by External Clock Generator VSS-0.3 0.5 V Driven by External Clock Generator 0.7VCC VCC+0.3 V VSS-0.3 0.2 VCC V VCC-0.4 V IOH = -0.5mA VCC-0.8 V IOH = -7mA 0.4 0.8 25 VDD -1.75 1 675 275 1.2 2.2 1 3 5 V V mV V IOL = 4.0mA IOL = 10mA Notes 5 2.0-3.6 -1 225 75 -1 A K K VIN = 0V, VCC Pull-ups disabled VIN = 0V; Pullups selected by mask option VIN = 0V, VCC at 8.0 MHz at 8.0 MHz 1, 2 1, 2 A mA mA PS022607-1205 DC Characteristics CrimzonTM ZLR32300 Product Specification 11 Table 9. LR32300 DC Characteristics (Continued) Symbol ICC1 ICC2 Parameter Standby Current (HALT Mode) Standby Current (STOP mode) VCC 2.0 3.6 2.0 3.6 2.0 3.6 TA= 0C to +70C Min Typ(7) Max 0.5 1.6 0.8 2.0 1.5 8 2.1 10 4.7 20 7.4 30 1.0 6 1.8 2.4 2.7 2.0 Units Conditions mA VIN = 0V, VCC at 8.0MHz mA Same as above VIN = 0 V, VCC WDT is not Running A A Same as above A VIN = 0 V, VCC WDT is Running A Same as above A Measured at 1.3V V V V 8MHz maximum Ext. CLK Freq. Notes 1, 2, 6 1, 2, 6 3 3 3 3 4 ILV VBO VLVD VHVD Standby Current (Low Voltage) VCC Low Voltage Protection Vcc Low Voltage Detection Vcc High Voltage Detection Notes: 1. All outputs unloaded, inputs at rail. 2. CL1 = CL2 = 100 pF. 3. Oscillator stopped. 4. Oscillator stops when VCC falls below VBO limit. 5. It is strongly recommended to add a filter capacitor (minimum 0.1 F), physically close to VDD and GND if operating voltage fluctuations are anticipated, such as those resulting from driving an Infrared LED. 6. Comparator and Timers are on. Interrupt disabled. 7. Typical values shoen are at 25 degrees C. PS022607-1205 DC Characteristics CrimzonTM ZLR32300 Product Specification 12 AC Characteristics Figure 7 and Table 10 describe the Alternating Current (AC) characteristics. 1 Clock 2 7 2 3 3 7 TIN 4 6 5 IRQN 8 9 Clock Setup 11 Stop Mode Recovery Source Figure 7. AC Timing Diagram 10 PS022607-1205 AC Characteristics CrimzonTM ZLR32300 Product Specification 13 Table 10. AC Characteristics TA=0C to +70C 8.0MHz Watch-Dog Timer Mode Register Units Notes (D1, D0) ns ns ns ns 1 1 1 1 1 1 100 100 70 10TpC 12 10TpC 2.0-3.6 2.0-3.6 2.0-3.6 2.0-3.6 2.0-3.6 2.0-3.6 10 20 40 160 2.5 10 5TpC ms ms ms ms ms ns ns ns 1 1, 2 1, 2 3 4 4 0, 0 0, 1 1, 0 1, 1 No Symbol 1 2 3 4 5 6 7 8 9 TpC TrC,TfC TwC TwTinL TwTinH TpTin Parameter Input Clock Period VCC 2.0-3.6 Minimum 121 Maximum DC 25 Clock Input Rise and 2.0-3.6 Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period 2.0-3.6 2.0 3.6 2.0-3.6 2.0-3.6 37 100 70 3TpC 8TpC TrTin,TfTin Timer Input Rise and 2.0-3.6 Fall Timers TwIL TwIH Interrupt Request Low Time Interrupt Request Input High Time Stop-Mode Recovery Width Spec Oscillator Start-Up Time Watch-Dog Timer Delay Time 2.0 3.6 2.0-3.6 2.0-3.6 10 Twsm 11 Tost 12 Twdt 13 TPOR Power-On Reset Notes: 1. Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0. 2. Interrupt request through Port 3 (P33-P31). 3. SMR - D5 = 1. 4. SMR - D5 = 0. PS022607-1205 AC Characteristics CrimzonTM ZLR32300 Product Specification 14 Pin Functions XTAL1 Crystal 1 (Time-Based Input) This pin connects a parallel-resonant crystal or ceramic resonator, to the on-chip oscillator input. Additionally, an optional external single-phase clock can be coded to the on-chip oscillator input. XTAL2 Crystal 2 (Time-Based Output) This pin connects a parallel-resonant, crystal or ceramic resonant to the on-chip oscillator output. Input/Output Ports Caution: The CMOS input buffer for each port 0, 1, or 2 pin is always connected to the pin, even when the pin is configured as an output. If the pin is configured as an open-drain output and no external signal is applied, a High output state can cause the CMOS input buffer to float. This might lead to excessive leakage current of more than 100 A. To prevent this leakage, connect the pin to an external signal with a defined logic level or ensure its output state is Low, especially during STOP mode. Internal pull-ups are disabled on any given pin or group of port pins when programmed into output mode. Port 0, 1, and 2 have both input and output capability. The input logic is always present no matter whether the port is configured as input or output. When doing a READ instruction, the MCU reads the actual value at the input logic but not from the output buffer. In addition, the instructions of OR, AND, and XOR have the Read-ModifyWrite sequence. The MCU first reads the port, and then modifies the value and load back to the port. Precaution must be taken if the port is configured as opendrain output or if the port is driving any circuit that makes the voltage different from the desired output logic. For example, pins P00-P07 are not connected to anything else. If it is configured as open-drain output with output logic as PS022607-1205 Pin Functions CrimzonTM ZLR32300 Product Specification 15 ONE, it is a floating port and reads back as ZERO. The following instruction sets P00-P07 all LOW. AND P0,#%F0 Port 0 (P07-P00) Port 0 is an 8-bit, bidirectional, CMOS-compatible port. These eight I/O lines are configured under software control as a nibble I/O port. The output drivers are push-pull or open-drain controlled by bit D2 in the PCON register. If one or both nibbles are needed for I/O operation, they must be configured by writing to the Port 0 mode register. After a hardware reset, Port 0 is configured as an input port. An optional pull-up transistor is available as a mask option on all Port 0 bits with nibble select. Note: The Port 0 direction is reset to be input following an SMR. PS022607-1205 Pin Functions CrimzonTM ZLR32300 Product Specification 16 4 ZLR32300 ROM Port 0 (I/O) 4 Open-Drain I/O Mask VCC Option Resistive Transistor Pull-up Pad Out In Figure 8. Port 0 Configuration Port 1 (P17-P10) Port 1 (see Figure 9) Port 1 can be configured for standard port input or output mode. After POR, Port 1 is configured as an input port. The output drivers are either push-pull or open-drain and are controlled by bit D1 in the PCON register. Notes: The Port 1 direction is reset to be input following an SMR. In 20 and 28-pin packages, Port 1 is reserved. A write to this register will have no effect and will always read FF. PS022607-1205 Pin Functions CrimzonTM ZLR32300 Product Specification 17 ZLR32300 ROM 8 Port 1 (I/O) Open-Drain OEN Mask Option VCC Resistive Transistor Pull-up Pad Out In Figure 9. Port 1 Configuration Port 2 (P27-P20) Port 2 is an 8-bit, bidirectional, CMOS-compatible I/O port (see Figure 10). These eight I/O lines can be independently configured under software control as inputs or outputs. Port 2 is always available for I/O operation. A mask option is available to connect eight pull-up transistors on this port. Bits programmed as outputs are globally programmed as either push-pull or open-drain. The POR resets with the eight bits of Port 2 configured as inputs. Port 2 also has an 8-bit input OR and AND gate, which can be used to wake up the part. P20 can be programmed to access the edge-detection circuitry in demodulation mode. PS022607-1205 Pin Functions CrimzonTM ZLR32300 Product Specification 18 ZLR32300 ROM Port 2 (I/O) Open-Drain I/O Mask VCC Option Resistive Transistor Pull-up Pad Out In Figure 10. Port 2 Configuration Port 3 (P37-P30) Port 3 is a 8-bit, CMOS-compatible fixed I/O port (see Figure 11). Port 3 consists of four fixed input (P33-P30) and four fixed output (P37-P34), which can be configured under software control for interrupt and as output from the counter/timers. P30, P31, P32, and P33 are standard CMOS inputs; P34, P35, P36, and P37 are push-pull outputs. PS022607-1205 Pin Functions CrimzonTM ZLR32300 Product Specification 19 Pref1/P30 P31 P32 P33 ZLR32300 ROM Port 3 (I/O) P34 P35 P36 P37 R247 = P3M D1 1 = Analog 0 = Digital P31 (AN1) Pref1 Dig. + - Comp1 IRQ2, P31 Data Latch An. P32 (AN2) P33 (REF2) + - Comp2 IRQ0, P32 Data Latch From STOP Mode Recovery Source of SMR IRQ1, P33 Data Latch Figure 11. Port 3 Configuration Two on-board comparators process analog signals on P31 and P32, with reference to the voltage on Pref1 and P33. The analog function is enabled by programming the Port 3 Mode Register (bit 1). P31 and P32 are programmable as rising, falling, or both edge triggered interrupts (IRQ register bits 6 and 7). Pref1 and P33 are the comparator reference voltage inputs. Access to the Counter Timer edge- PS022607-1205 Pin Functions CrimzonTM ZLR32300 Product Specification 20 detection circuit is through P31 or P20 (see T8 and T16 Common Functions-- CTR1(0D)01h on page 32). Other edge detect and IRQ modes are described in Table 11. Note: Comparators are powered down by entering STOP mode. For P31-P33 to be used in a STOP Mode Recovery (SMR) source, these inputs must be placed into digital mode. 2 Table 11. Port 3 Pin Function Summary Pin Pref1/P30 P31 P32 P33 P34 P35 P36 P37 P20 I/O IN IN IN IN OUT OUT OUT OUT I/O IN T8 T16 T8/16 AO2 IN Counter/Timers Comparator RF1 AN1 AN2 RF2 AO1 IRQ2 IRQ0 IRQ1 Interrupt Port 3 also provides output for each of the counter/timers and the AND/OR Logic (see Figure 12). Control is performed by programming bits D5-D4 of CTR1, bit 0 of CTR0, and bit 0 of CTR2. PS022607-1205 Pin Functions CrimzonTM ZLR32300 Product Specification 21 CTR0, D0 P34 data PCON, D0 MUX T8_Out VDD Pad P34 MUX P3M D1 P31 P31 P30 (Pref1) + Comp1 CTR2, D0 Out 35 T16_Out VDD MUX Pad P35 CTR1, D6 Out 36 T8/T16_Out VDD Pad P36 MUX PCON, D0 P37 data VDD Pad P37 MUX P3M D1 P32 P32 P33 + Comp2 Figure 12. Port 3 Counter/Timer Output Configuration PS022607-1205 Pin Functions CrimzonTM ZLR32300 Product Specification 22 Comparator Inputs In analog mode, P31 and P32 have a comparator front end. The comparator reference is supplied to P33 and Pref1. In this mode, the P33 internal data latch and its corresponding IRQ1 are diverted to the SMR sources (excluding P31, P32, and P33) as indicated in Figure 11 on page 19. In digital mode, P33 is used as D3 of the Port 3 input register, which then generates IRQ1. Note: Comparators are powered down by entering STOP mode. For P31-P33 to be used in a STOP mode Recovery source, these inputs must be placed into digital mode. Comparator Outputs These channels can be programmed to be output on P34 and P37 through the PCON register. RESET (Input, Active Low) Reset initializes the MCU and is accomplished either through Power-On, WatchDog Timer, STOP mode Recovery, Low-Voltage detection, or external reset. During Power-On Reset and Watch-Dog Timer Reset, the internally generated reset drives the reset pin Low for the POR time. Any devices driving the external reset line must be open-drain to avoid damage from a possible conflict during reset conditions. Pull-up is provided internally. When the ZLR32300 asserts (Low) the RESET pin, the internal pull-up is disabled. The ZLR32300 does not assert the RESET pin when under VBO. Note: The external Reset does not initiate an exit from STOP mode. Functional Description This device incorporates special functions to enhance the Z8(R)' functionality in consumer and battery-operated applications. Program Memory This device addresses 32KB of ROM memory. The first 12 Bytes are reserved for interrupt vectors. These locations contain the six 16-bit vectors that correspond to the six available interrupts. See Figure 13. RAM This device features 256B of RAM. PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 23 Location of first Byte of instruction executed after RESET 32768 Not Accessible On-Chip ROM 12 11 10 9 8 7 Reset Start Address IRQ5 IRQ5 IRQ4 IRQ4 IRQ3 IRQ3 IRQ2 IRQ2 IRQ1 IRQ1 IRQ0 IRQ0 Interrupt Vector (Lower Byte) 6 5 4 Interrupt Vector (Upper Byte) 3 2 1 0 Figure 13. Program Memory Map (32K ROM) Expanded Register File The register file has been expanded to allow for additional system control registers and for mapping of additional peripheral devices into the register address area. The Z8(R) register address space (R0 through R15) has been implemented as 16 banks, with 16 registers per bank. These register groups are known as the PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 24 ERF (Expanded Register File). Bits 7-4 of register RP select the working register group. Bits 3-0 of register RP select the expanded register file bank. Note: An expanded register bank is also referred to as an expanded register group (see Figure 14). PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 25 Z8(R) Standard Control Registers FF FE SPL SPH RP FLAGS IMR IRQ IPR P01M P3M P2M Reserved Reserved Reserved Reserved Reserved Reserved Reset Condition Expanded Reg. Bank 0/Group 15** D7 D6 D5 D4 D3 D2 D1 D0 UUUUUUUU UUUUUUUU 00000000 UUUUUUUU UUUUUUUU 00000000 UUUUUUUU 11001111 00000000 11111111 UUUUUUUU UUUUUUUU UUUUUUUU UUUUUUUU UUUUUUUU UUUUUUUU Register Pointer 76543210 Working Register Group Pointer Expanded Register Bank Pointer * * FD FC FB FA F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 Register File (Bank 0)** FF F0 Expanded Reg. Bank F/Group 0** * * (F) 0F WDTMR (F) 0E Reserved (F) 0D SMR2 (F) 0C Reserved 7F (F) 0B SMR (F) 0A Reserved (F) 09 Reserved (F) 08 Reserved (F) 07 Reserved (F) 06 Reserved (F) 05 Reserved 0F 00 (F) 04 Reserved (F) 03 Reserved (F) 02 Reserved (F) 01 Reserved Expanded Reg. Bank 0/Group (0) (0) 03 P3 (0) 02 P2 * (0) 01 P1 (0) 00 P0 U = Unknown * Not reset with a Stop-Mode Recovery. P1 reserved in 20 and 28-pin package. ** All addresses are in hexadecimal Is not reset with a Stop-Mode Recovery, except Bit 0 Bit 5 Is not reset with a Stop-Mode Recovery Bits 5,4,3,2 not reset with a Stop-Mode Recovery Bits 5 and 4 not reset with a Stop-Mode Recovery Bits 5,4,3,2,1 not reset with a Stop-Mode Recovery 0 U U U U * (F) 00 PCON 11111110 U01000U0 00000000 UU001101 Expanded Reg. Bank D/Group 0 (D) 0C * * * * * * * * (D) 0B (D) 0A (D) 09 (D) 08 (D) 07 (D) 06 (D) 05 (D) 04 (D) 03 (D) 02 (D) 01 (D) 00 LVD HI8 LO8 HI16 LO16 TC16H TC16L TC8H TC8L CTR3 CTR2 CTR1 CTR0 UUUUUUU0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00011111 00000000 00000000 00000000 Figure 14. Expanded Register File Architecture PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 26 The upper nibble of the register pointer (see Figure 15) selects which working register group, of 16 bytes in the register file, is accessed out of the possible 256. The lower nibble selects the expanded register file bank and, in the case of the CrimzonTM ZLR32300 family, banks 0, F, and D are implemented. A 0h in the lower nibble allows the normal register file (bank 0) to be addressed. Any other value from 1h to Fh exchanges the lower 16 registers to an expanded register bank. R253 RP D7 D6 D5 D4 D3 D2 D1 D0 Expanded Register File Pointer Working Register Pointer Default Setting After Reset = 0000 0000 Figure 15. Register Pointer Example: CrimzonTM ZLR32300: (See Figure 14 on page 25) R253 RP = 00h R0 = Port 0 R1 = Port 1 R2 = Port 2 R3 = Port 3 But if: R253 RP = 0Dh R0 = CTR0 R1 = CTR1 R2 = CTR2 R3 = CTR3 PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 27 The counter/timers are mapped into ERF group D. Access is easily performed using the following: LD for access to bank D register group 0) LD LD LD LD for access to bank D RP, #0Dh ; Select ERF D ; (working R0,#xx 1, #xx R1, 2 RP, #0Dh ; load CTR0 ; load CTR1 ; CTR2CTR1 ; Select ERF D ; (working register group 0) LD RP, #7Dh expanded register bank D and working group 7 of bank 0 for access. LD 71h, 2 ; CTR2register 71h LD R1, 2 ; CTR2register 71h ; Select ; register Register File The register file (bank 0) consists of 4 I/O port registers, 237 general-purpose registers, 16 control and status registers (R0-R3, R4-R239, and R240-R255, respectively), and two expanded registers groups in Banks D (see Table 12) and F. Instructions can access registers directly or indirectly through an 8-bit address field, thereby allowing a short, 4-bit register address to use the Register Pointer (Figure 16). In the 4-bit mode, the register file is divided into 16 working register groups, each occupying 16 continuous locations. The Register Pointer addresses the starting location of the active working register group. Note: Working register group E0-EF can only be accessed through working registers and indirect addressing modes. PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 28 R7 R6 R5 R4 R3 R2 R1 R R253 The upper nibble of the register file address provided by the register pointer specifies the active working-register group. FF F0 EF E0 DF D0 40 3F 30 2F 20 1F Register Group 1 10 0F 00 Register Group 0 I/O Ports Specified Working Register Group Register Group 2 The lower nibble of the register file address provided by the instruction points to the specified register. R15 to R0 R15 to R4 * R3 to R0 * * RP = 00: Selects Register Bank 0, Working Register Group 0 Figure 16. Register Pointer--Detail Stack The internal register file is used for the stack. An 8-bit Stack Pointer SPL (R255) is used for the internal stack that resides in the general-purpose registers (R4- R239). SPH (R254) can be used as a general-purpose register. PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 29 Timers T8_Capture_HI--HI8(D)0BH This register holds the captured data from the output of the 8-bit Counter/Timer0. Typically, this register holds the number of counts when the input signal is 1. Field T8_Capture_HI Bit Position [7:0] R/W Description Captured Data - No Effect T8_Capture_LO--L08(D)0AH This register holds the captured data from the output of the 8-bit Counter/Timer0. Typically, this register holds the number of counts when the input signal is 0. Field T8_Capture_L0 Bit Position [7:0] R/W Description Captured Data - No Effect T16_Capture_HI--HI16(D)09H This register holds the captured data from the output of the 16-bit Counter/ Timer16. This register holds the MS-Byte of the data. Field Bit Position R/W Description Captured Data - No Effect T16_Capture_HI [7:0] T16_Capture_LO--L016(D)08H This register holds the captured data from the output of the 16-bit Counter/ Timer16. This register holds the LS-Byte of the data. Field Bit Position Description R/W Captured Data - No Effect T16_Capture_LO [7:0] Counter/Timer2 MS-Byte Hold Register--TC16H(D)07H Field T16_Data_HI Bit Position [7:0] R/W Description Data PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 30 Counter/Timer2 LS-Byte Hold Register--TC16L(D)06H Field T16_Data_LO Bit Position [7:0] R/W Description Data Counter/Timer8 High Hold Register--TC8H(D)05H Field T8_Level_HI Bit Position [7:0] R/W Description Data Counter/Timer8 Low Hold Register--TC8L(D)04H Field T8_Level_LO Bit Position [7:0] R/W Description Data CTR0 Counter/Timer8 Control Register--CTR0(D)00H Table 12 lists and briefly describes the fields for this register. Table 12. CTR0(D)00H Counter/Timer8 Control Register Field T8_Enable Bit Position 7------R/W Value 0* 1 0 1 0* 1 0** 1 0 1 0 0** 01 10 11 0** 1 Description Counter Disabled Counter Enabled Stop Counter Enable Counter Modulo-N Single Pass No Counter Time-Out Counter Time-Out Occurred No Effect Reset Flag to 0 SCLK SCLK/2 SCLK/4 SCLK/8 Disable Data Capture Interrupt Enable Data Capture Interrupt Single/Modulo-N Time_Out -6--------5------ R/W R/W T8 _Clock ---43--- R/W Capture_INT_Mask -----2-- R/W PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 31 Table 12. CTR0(D)00H Counter/Timer8 Control Register (Continued) Field Counter_INT_Mask P34_Out Bit Position ------1-------0 R/W R/W Value 0** 1 0* 1 Description Disable Time-Out Interrupt Enable Time-Out Interrupt P34 as Port Output T8 Output on P34 Note: *Indicates the value upon Power-On Reset. **Indicates the value upon Power-On Reset. Not reset with a Stop Mode recovery. T8 Enable This field enables T8 when set (written) to 1. Single/Modulo-N When set to 0 (Modulo-N), the counter reloads the initial value when the terminal count is reached. When set to 1 (single-pass), the counter stops when the terminal count is reached. Timeout This bit is set when T8 times out (terminal count reached). To reset this bit, write a 1 to its location. Caution: Writing a 1 is the only way to reset the Terminal Count status condition. Reset this bit before using/enabling the counter/timers. The first clock of T8 might not have complete clock width and can occur any time when enabled. Note: Take care when using the OR or AND commands to manipulate CTR0, bit 5 and CTR1, bits 0 and 1 (Demodulation Mode). These instructions use a Read-Modify-Write sequence in which the current status from the CTR0 and CTR1 registers is ORed or ANDed with the designated value and then written back into the registers. T8 Clock These bits define the frequency of the input signal to T8. PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 32 Capture_INT_Mask Set this bit to allow an interrupt when data is captured into either LO8 or HI8 upon a positive or negative edge detection in demodulation mode. Counter_INT_Mask Set this bit to allow an interrupt when T8 has a timeout. P34_Out This bit defines whether P34 is used as a normal output pin or the T8 output. T8 and T16 Common Functions--CTR1(0D)01h This register controls the functions in common with the T8 and T16. Table 13 lists and briefly describes the fields for this register. Table 13. CTR1(0D)01H T8 and T16 Common Functions Field Mode P36_Out/ Demodulator_Input Bit Position 7-------6-----R/W R/W 0* 1 0* 1 T8/T16_Logic/ Edge _Detect --54---R/W 00** 01 10 11 00** 01 10 11 Value 0* 1 Description Transmit Mode Demodulation Mode Transmit Mode Port Output T8/T16 Output Demodulation Mode P31 P20 Transmit Mode AND OR NOR NAND Demodulation Mode Falling Edge Rising Edge Both Edges Reserved PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 33 Table 13. CTR1(0D)01H T8 and T16 Common Functions (Continued) Field Transmit_Submode/ Glitch_Filter Bit Position ----32-Value R/W 00 01 10 11 00 01 10 11 Initial_T8_Out/ Rising Edge ------1R/W 0 1 0 1 0 1 0 1 0 1 0 1 Description Transmit Mode Normal Operation Ping-Pong Mode T16_Out = 0 T16_Out = 1 Demodulation Mode No Filter 4 SCLK Cycle 8 SCLK Cycle Reserved Transmit Mode T8_OUT is 0 Initially T8_OUT is 1 Initially Demodulation Mode No Rising Edge Rising Edge Detected No Effect Reset Flag to 0 Transmit Mode T16_OUT is 0 Initially T16_OUT is 1 Initially Demodulation Mode No Falling Edge Falling Edge Detected No Effect Reset Flag to 0 R W Initial_T16_Out/ Falling_Edge -------0 R/W R W Note: *Default at Power-On Reset. **Default at Power-On Reset.Not reset with a Stop Mode recovery. Mode If the result is 0, the counter/timers are in TRANSMIT mode; otherwise, they are in DEMODULATION mode. P36_Out/Demodulator_Input In TRANSMIT Mode, this bit defines whether P36 is used as a normal output pin or the combined output of T8 and T16. In DEMODULATION Mode, this bit defines whether the input signal to the Counter/Timers is from P20 or P31. If the input signal is from Port 31, a capture event may also generate an IRQ2 interrupt. To prevent generating an IRQ2, either disable the IRQ2 interrupt by clearing its IMR bit D2 or use P20 as the input. PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 34 T8/T16_Logic/Edge _Detect In TRANSMIT Mode, this field defines how the outputs of T8 and T16 are combined (AND, OR, NOR, NAND). In DEMODULATION Mode, this field defines which edge should be detected by the edge detector. Transmit_Submode/Glitch Filter In Transmit Mode, this field defines whether T8 and T16 are in the PING-PONG mode or in independent normal operation mode. Setting this field to "NORMAL OPERATION Mode" terminates the "PING-PONG Mode" operation. When set to 10, T16 is immediately forced to a 0; a setting of 11 forces T16 to output a 1. In DEMODULATION Mode, this field defines the width of the glitch that must be filtered out. Initial_T8_Out/Rising_Edge In TRANSMIT Mode, if 0, the output of T8 is set to 0 when it starts to count. If 1, the output of T8 is set to 1 when it starts to count. When the counter is not enabled and this bit is set to 1 or 0, T8_OUT is set to the opposite state of this bit. This ensures that when the clock is enabled, a transition occurs to the initial state set by CTR1, D1. In DEMODULATION Mode, this bit is set to 1 when a rising edge is detected in the input signal. In order to reset the mode, a 1 should be written to this location. Initial_T16 Out/Falling _Edge In TRANSMIT Mode, if it is 0, the output of T16 is set to 0 when it starts to count. If it is 1, the output of T16 is set to 1 when it starts to count. This bit is effective only in Normal or PING-PONG Mode (CTR1, D3; D2). When the counter is not enabled and this bit is set, T16_OUT is set to the opposite state of this bit. This ensures that when the clock is enabled, a transition occurs to the initial state set by CTR1, D0. In DEMODULATION Mode, this bit is set to 1 when a falling edge is detected in the input signal. In order to reset it, a 1 should be written to this location. Note: Modifying CTR1 (D1 or D0) while the counters are enabled causes unpredictable output from T8/16_OUT. CTR2 Counter/Timer 16 Control Register--CTR2(D)02H Table 14 lists and briefly describes the fields for this register. PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 35 Table 14. CTR2(D)02H: Counter/Timer16 Control Register Field T16_Enable Bit Position 7------R W Single/Modulo-N -6-----R/W 0* 1 0 1 Time_Out --5----R 0** 1 0 1 00** 01 10 11 0** 1 0* 1 0* 1 Value 0* 1 0 1 Description Counter Disabled Counter Enabled Stop Counter Enable Counter Transmit Mode Modulo-N Single Pass Demodulation Mode T16 Recognizes Edge T16 Does Not Recognize Edge No Counter Timeout Counter Timeout Occurred No Effect Reset Flag to 0 SCLK SCLK/2 SCLK/4 SCLK/8 Disable Data Capture Int. Enable Data Capture Int. Disable Timeout Int. Enable Timeout Int. P35 as Port Output T16 Output on P35 W T16 _Clock ---43--R/W Capture_INT_Mask Counter_INT_Mask P35_Out -----2-------1-------0 R/W R/W R/W Note: *Indicates the value upon Power-On Reset. **Indicates the value upon Power-On Reset. Not reset with a Stop Mode recovery. T16_Enable This field enables T16 when set to 1. Single/Modulo-N In TRANSMIT Mode, when set to 0, the counter reloads the initial value when it reaches the terminal count. When set to 1, the counter stops when the terminal count is reached. PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 36 In DEMODULATION Mode, when set to 0, T16 captures and reloads on detection of all the edges. When set to 1, T16 captures and detects on the first edge but ignores the subsequent edges. For details, see the description of T16 Demodulation Mode on page 44. Time_Out This bit is set when T16 times out (terminal count reached). To reset the bit, write a 1 to this location. T16_Clock This bit defines the frequency of the input signal to Counter/Timer16. Capture_INT_Mask This bit is set to allow an interrupt when data is captured into LO16 and HI16. Counter_INT_Mask Set this bit to allow an interrupt when T16 times out. P35_Out This bit defines whether P35 is used as a normal output pin or T16 output. CTR3 T8/T16 Control Register--CTR3(D)03H Table 15 lists and briefly describes the fields for this register. This register allows the T8 and T16 counters to be synchronized. Table 15. CTR3 (D)03H: T8/T16 Control Register Field T16 Enable Bit Position 7------R R W W R R W W R/W Value 0** 1 0 1 0** 1 0 1 0* 1 Description Counter Disabled Counter Enabled Stop Counter Enable Counter Counter Disabled Counter Enabled Stop Counter Enable Counter Disable Sync Mode Enable Sync Mode T8 Enable -6------ Sync Mode --5----- PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 37 Table 15. CTR3 (D)03H: T8/T16 Control Register (Continued) Field Reserved Bit Position ---43210 R W Value 1 x Description Always reads 11111 No Effect Note: *Indicates the value upon Power-On Reset. **Indicates the value upon Power-On Reset. Not reset with a Stop Mode recovery. Counter/Timer Functional Blocks Input Circuit The edge detector monitors the input signal on P31 or P20. Based on CTR1 D5- D4, a pulse is generated at the Pos Edge or Neg Edge line when an edge is detected. Glitches in the input signal that have a width less than specified (CTR1 D3, D2) are filtered out (see Figure 17). CTR1 D5,D4 P31 MUX P20 Glitch Filter Edge Detector Pos Edge Neg Edge CTR1 D6 CTR1 D3, D2 Figure 17. Glitch Filter Circuitry T8 Transmit Mode Before T8 is enabled, the output of T8 depends on CTR1, D1. If it is 0, T8_OUT is 1; if it is 1, T8_OUT is 0. See Figure 18. PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 38 T8 (8-Bit) Transmit Mode No T8_Enable Bit Set CTR0, D7 Yes Reset T8_Enable Bit 0 Load TC8L Reset T8_OUT CTR1, D1 Value 1 Load TC8H Set T8_OUT Set Timeout Status Bit (CTR0 D5) and Generate Timeout_Int if Enabled Enable T8 No T8_Timeout Yes Single Pass Single Pass? Modulo-N 1 Load TC8L Reset T8_OUT T8_OUT Value 0 Load TC8H Set T8_OUT Enable T8 Set Timeout Status Bit (CTR0 D5) and Generate Timeout_Int if Enabled No T8_Timeout Yes Figure 18. Transmit Mode Flowchart PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 39 When T8 is enabled, the output T8_OUT switches to the initial value (CTR1, D1). If the initial value (CTR1, D1) is 0, TC8L is loaded; otherwise, TC8H is loaded into the counter. In SINGLE-PASS Mode (CTR0, D6), T8 counts down to 0 and stops, T8_OUT toggles, the timeout status bit (CTR0, D5) is set, and a timeout interrupt can be generated if it is enabled (CTR0, D1). In Modulo-N Mode, upon reaching terminal count, T8_OUT is toggled, but no interrupt is generated. From that point, T8 loads a new count (if the T8_OUT level now is 0), TC8L is loaded; if it is 1, TC8H is loaded. T8 counts down to 0, toggles T8_OUT, and sets the timeout status bit (CTR0, D5), thereby generating an interrupt if enabled (CTR0, D1). One cycle is thus completed. T8 then loads from TC8H or TC8L according to the T8_OUT level and repeats the cycle. See Figure 19. Z8(R) Data Bus Positive Edge Negative Edge HI8 LO8 CTR0 D1 IRQ4 CTR0 D2 CTR0 D4, D3 Clock Select Clock 8-Bit Counter T8 SCLK T8_OUT TC8H Z8(R) Data Bus TC8L Figure 19. 8-Bit Counter/Timer Circuits You can modify the values in TC8H or TC8L at any time. The new values take effect when they are loaded. Caution: To ensure known operation do not write these registers at the time the values are to be loaded into the counter/timer. PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 40 An initial count of 1 is not allowed (a non-function occurs). An initial count of 0 causes TC8 to count from 0 to FFH to FEH. Note: The letter H denotes hexadecimal values. Transition from 0 to FFH is not a timeout condition. Caution: Using the same instructions for stopping the counter/timers and setting the status bits is not recommended. Two successive commands are necessary. First, the counter/timers must be stopped. Second, the status bits must be reset. These commands are required because it takes one counter/timer clock interval for the initiated event to actually occur. See Figure 20 and Figure 21. TC8H Counts Counter Enable Command; T8_OUT Switches to Its Initial Value (CTR1 D1) T8_OUT Toggles; Timeout Interrupt Figure 20. T8_OUT in Single-Pass Mode T8_OUT Toggles ... T8_OUT TC8L TC8H TC8L TC8H TC8L Counter Enable Command; T8_OUT Switches to Its Initial Value (CTR1 D1) Timeout Interrupt Timeout Interrupt Figure 21. T8_OUT in Modulo-N Mode T8 Demodulation Mode The user must program TC8L and TC8H to FFh. After T8 is enabled, when the first edge (rising, falling, or both depending on CTR1, D5; D4) is detected, it starts to PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 41 count down. When a subsequent edge (rising, falling, or both depending on CTR1, D5; D4) is detected during counting, the current value of T8 is complemented and put into one of the capture registers. If it is a positive edge, data is put into LO8; if it is a negative edge, data is put into HI8. From that point, one of the edge detect status bits (CTR1, D1; D0) is set, and an interrupt can be generated if enabled (CTR0, D2). Meanwhile, T8 is loaded with FFh and starts counting again. If T8 reaches 0, the timeout status bit (CTR0, D5) is set, and an interrupt can be generated if enabled (CTR0, D1). T8 then continues counting from FFh (see Figure 22 and Figure 23). T8 (8-Bit) Count Capture No T8 Enable (Set by User) Yes No Edge Present Yes What Kind of Edge Positive Negative T8 LO8 T8 HI8 FFh T8 Figure 22. Demodulation Mode Count Capture Flowchart PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 42 T8 (8-Bit) Demodulation Mode No T8 Enable CTR0, D7 Yes FFh TC8 No First Edge Present Yes Disable TC8 Enable TC8 No T8_Enable Bit Set Yes No Edge Present Yes Set Edge Present Status Bit and Trigger Data Capture Int. If Enabled T8 Timeout Yes Set Timeout Status Bit and Trigger Timeout Int. If Enabled No Continue Counting Figure 23. Demodulation Mode Flowchart PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 43 T16 Transmit Mode In NORMAL or PING-PONG mode, the output of T16 when not enabled, is dependent on CTR1, D0. If it is a 0, T16_OUT is a 1; if it is a 1, T16_OUT is 0. You can force the output of T16 to either a 0 or 1 whether it is enabled or not by programming CTR1 D3; D2 to a 10 or 11. When T16 is enabled, TC16H * 256 + TC16L is loaded, and T16_OUT is switched to its initial value (CTR1, D0). When T16 counts down to 0, T16_OUT is toggled (in NORMAL or PING-PONG mode), an interrupt (CTR2, D1) is generated (if enabled), and a status bit (CTR2, D5) is set. See Figure 24. Z8(R) Data Bus Positive Edge Negative Edge HI16 LO16 CTR2 D1 IRQ3 CTR2 D2 CTR2 D4, D3 Clock Select Clock 16-Bit Counter T16 SCLK T16_OUT TC16H Z8(R) Data Bus TC16L Figure 24. 16-Bit Counter/Timer Circuits Note: Global interrupts override this function as described in Interrupts on page 47. If T16 is in SINGLE-PASS mode, it is stopped at this point (see Figure 25). If it is in Modulo-N Mode, it is loaded with TC16H * 256 + TC16L, and the counting continues (see Figure 26). You can modify the values in TC16H and TC16L at any time. The new values take effect when they are loaded. PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 44 Caution: Do not load these registers at the time the values are to be loaded into the counter/timer to ensure known operation. An initial count of 1 is not allowed. An initial count of 0 causes T16 to count from 0 to FFFFH to FFFEH. Transition from 0 to FFFFH is not a timeout condition. TC16H*256+TC16L Counts "Counter Enable" Command T16_OUT Switches to Its Initial Value (CTR1 D0) T16_OUT Toggles, Timeout Interrupt Figure 25. T16_OUT in Single-Pass Mode TC16H*256+TC16L TC16_OUT TC16H*256+TC16L TC16H*256+TC16L ... "Counter Enable" Command, T16_OUT Switches to Its Initial Value (CTR1 D0) T16_OUT Toggles, Timeout Interrupt T16_OUT Toggles, Timeout Interrupt Figure 26. T16_OUT in Modulo-N Mode T16 DEMODULATION Mode The user must program TC16L and TC16H to FFH. After T16 is enabled, and the first edge (rising, falling, or both depending on CTR1 D5; D4) is detected, T16 captures HI16 and LO16, reloads, and begins counting. If D6 of CTR2 Is 0 When a subsequent edge (rising, falling, or both depending on CTR1, D5; D4) is detected during counting, the current count in T16 is complemented and put into HI16 and LO16. When data is captured, one of the edge detect status bits (CTR1, D1; D0) is set, and an interrupt is generated if enabled (CTR2, D2). T16 is loaded with FFFFH and starts again. This T16 mode is generally used to measure space time, the length of time between bursts of carrier signal (marks). PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 45 If D6 of CTR2 Is 1 T16 ignores the subsequent edges in the input signal and continues counting down. A timeout of T8 causes T16 to capture its current value and generate an interrupt if enabled (CTR2, D2). In this case, T16 does not reload and continues counting. If the D6 bit of CTR2 is toggled (by writing a 0 then a 1 to it), T16 captures and reloads on the next edge (rising, falling, or both depending on CTR1, D5; D4), continuing to ignore subsequent edges. This T16 mode generally measures mark time, the length of an active carrier signal burst. If T16 reaches 0, T16 continues counting from FFFFH. Meanwhile, a status bit (CTR2 D5) is set, and an interrupt timeout can be generated if enabled (CTR2 D1). Ping-Pong Mode This operation mode is only valid in TRANSMIT Mode. T8 and T16 must be programmed in Single-Pass mode (CTR0, D6; CTR2, D6), and Ping-Pong mode must be programmed in CTR1, D3; D2. The user can begin the operation by enabling either T8 or T16 (CTR0, D7 or CTR2, D7). For example, if T8 is enabled, T8_OUT is set to this initial value (CTR1, D1). According to T8_OUT's level, TC8H or TC8L is loaded into T8. After the terminal count is reached, T8 is disabled, and T16 is enabled. T16_OUT then switches to its initial value (CTR1, D0), data from TC16H and TC16L is loaded, and T16 starts to count. After T16 reaches the terminal count, it stops, T8 is enabled again, repeating the entire cycle. Interrupts can be allowed when T8 or T16 reaches terminal control (CTR0, D1; CTR2, D1). To stop the ping-pong operation, write 00 to bits D3 and D2 of CTR1. See Figure 27. Note: Enabling ping-pong operation while the counter/timers are running might cause intermittent counter/timer function. Disable the counter/timers and reset the status flags before instituting this operation. PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 46 Enable TC8 Enable Timeout Ping-Pong CTR1 D3,D2 TC16 Timeout Figure 27. Ping-Pong Mode Diagram Initiating PING-PONG Mode First, make sure both counter/timers are not running. Set T8 into Single-Pass mode (CTR0, D6), set T16 into SINGLE-PASS mode (CTR2, D6), and set the Ping-Pong mode (CTR1, D2; D3). These instructions can be in random order. Finally, start PING-PONG mode by enabling either T8 (CTR0, D7) or T16 (CTR2, D7). See Figure 28. P34_Internal MUX P34 CTR0 D0 T8_OUT T16_OUT CTR1, D2 CTR1 D5, D4 CTR1 D3 CTR2 D0 Figure 28. Output Circuit P35_Internal P36_Internal AND/OR/NOR/NAND Logic MUX CTR1 D6 MUX P35 P36 MUX The initial value of T8 or T16 must not be 1. If you stop the timer and restart the timer, reload the initial value to avoid an unknown previous value. PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 47 During PING-PONG Mode The enable bits of T8 and T16 (CTR0, D7; CTR2, D7) are set and cleared alternately by hardware. The timeout bits (CTR0, D5; CTR2, D5) are set every time the counter/timers reach the terminal count. Timer Output The output logic for the timers is illustrated in Figure 28. P34 is used to output T8OUT when D0 of CTR0 is set. P35 is used to output the value of TI6-OUT when D0 of CTR2 is set. When D6 of CTR1 is set, P36 outputs the logic combination of T8-OUT and T16-OUT determined by D5 and D4 of CTR1. Interrupts The CrimzonTM ZLR32300 features six different interrupts (Table 16). The interrupts are maskable and prioritized (Figure 29). The six sources are divided as follows: three sources are claimed by Port 3 lines P33-P31, two by the counter/ timers (Table 16) and one for low voltage detection. The Interrupt Mask Register (globally or individually) enables or disables the six interrupt requests. The source for IRQ is determined by bit 1 of the Port 3 mode register (P3M). When in digital mode, Pin P33 is the source. When in analog mode the output of the stop mode recovery source logic is used as the source for the interrupt. See Figure 34. PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 48 P33 STOP Mode Recovery Source 0 1 D1 of P3M Register P31 P32 IRQ Register D6, D7 Interrupt Edge Select IRQ2 IRQ0 IRQ1 Timer 16 IRQ3 Timer 8 Low-Voltage Detection IRQ5 IRQ4 IRQ IMR 5 IPR Global Interrupt Enable Interrupt Request Priority Logic Vector Select Figure 29. Interrupt Block Diagram PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 49 Table 16. Interrupt Types, Sources, and Vectors Name IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Source P32 P33 Vector Location 0,1 2,3 Comments External (P32), Rising, Falling Edge Triggered External (P33), Falling Edge Triggered External (P31), Rising, Falling Edge Triggered Internal Internal Internal P31, TIN 4,5 T16 T8 LVD 6,7 8,9 10,11 When more than one interrupt is pending, priorities are resolved by a programmable priority encoder controlled by the Interrupt Priority Register. An interrupt machine cycle activates when an interrupt request is granted. As a result, all subsequent interrupts are disabled, and the Program Counter and Status Flags are saved. The cycle then branches to the program memory vector location reserved for that interrupt. All CrimzonTM ZLR32300 interrupts are vectored through locations in the program memory. This memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked, and the Interrupt Request register is polled to determine which of the interrupt requests require service. An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is mapped into IRQ0. Interrupts IRQ2 and IRQ0 can be rising, falling, or both edge triggered. These interrupts are programmable by the user. The software can poll to identify the state of the pin. Programming bits for the Interrupt Edge Select are located in the IRQ Register (R250), bits D7 and D6. The configuration is indicated in Table 17. Table 17. IRQ Register IRQ D7 0 0 1 1 D6 0 1 0 1 Interrupt Edge IRQ2 (P31) F F R R/F IRQ0 (P32) F R F R/F Note: F = Falling Edge; R = Rising Edge PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 50 Clock The device's on-chip oscillator has a high-gain, parallel-resonant amplifier, for connection to a crystal, ceramic resonator, or any suitable external clock source (XTAL1 = Input, XTAL2 = Output). The crystal must be AT cut, 1 MHz to 8 MHz maximum, with a series resistance (RS) less than or equal to 100 . The on-chip oscillator can be driven with a suitable external clock source. The crystal must be connected across XTAL1 and XTAL2 using the recommended capacitors from each pin to ground. The typical capacitor value is 10pF for 8MHz. Also check with the crystal supplier for the optimum capacitance. XTAL1 C1 XTAL1 XTAL1 XTAL2 C2 XTAL2 XTAL2 Crystal C1, C2 = 10 pF * f = 8 MHz External Clock Ceramic Resonator f = 8 MHz *Note: preliminary value. Figure 30. Oscillator Configuration ZiLOG IR MCU supports crystal, resonator, and oscillator. Most resonators have a frequency tolerance of less than 0.5%, which is enough for remote control application. Resonator has a very fast startup time, which is around few hundred microseconds. Most crystals have a frequency tolerance of less than 50 ppm (0.005%). However, crystal needs longer startup time than the resonator. The large loading capacitance slows down the oscillation startup time. ZiLOG suggests not to use more than 10pF loading capacitor for the crystal. If the stray capacitance of the PCB or the crystal is high, the loading capacitance C1 and C2 must be reduced further to ensure stable oscillation before the TPOR (Power-On Reset time is typically 5-6 ms. Refer to AC Characteristics in Table 10). For Stop Mode Recovery operation, bit 5 of SMR register allows you to select the STOP mode recovery delay, which is the TPOR. If STOP mode recovery delay is not selected, the MCU executes instruction immediately after it wakes up from the PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 51 STOP mode. If resonator or crystal is used as a clock source then STOP mode recovery delay needs to be selected (bit 5 of SMR = 1). For both resonator and crystal oscillator, the oscillation ground must go directly to the ground pin of the microcontroller. The oscillation ground must use the shortest distance from the microcontroller ground pin and it must be isolated from other connections. Power Management Power-On Reset A timer circuit clocked by a dedicated on-board RC-oscillator is used for the Power-On Reset (POR) timer function. The POR time allows VDD and the oscillator circuit to stabilize before instruction execution begins. The POR timer circuit is a one-shot timer triggered by one of three conditions: * * * Power Fail to Power OK status, including Waking up from VBO Standby Stop-Mode Recovery (if D5 of SMR = 1) WDT Timeout The POR timer is 2.5 ms minimum. Bit 5 of the Stop-Mode Register determines whether the POR timer is bypassed after Stop-Mode Recovery (typical for external clock). HALT Mode This instruction turns off the internal CPU clock, but not the XTAL oscillation. The counter/timers and external interrupts IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, and IRQ5 remain active. The devices are recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT Mode. After the interrupt service routine, the program continues from the instruction after HALT Mode. STOP Mode This instruction turns off the internal clock and external crystal oscillation, reducing the standby current to 10 A or less. STOP Mode is terminated only by a reset, such as WDT timeout, POR, SMR or external reset. This condition causes the processor to restart the application program at address 000CH. To enter STOP (or HALT) mode, first flush the instruction pipeline to avoid suspending execution in mid-instruction. Execute a NOP (Opcode = FFH) immediately before the appropriate sleep instruction, as follows: PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 52 FF 6F NOP STOP ; clear the pipeline ; enter STOP mode or FF 7F NOP HALT ; clear the pipeline ; enter HALT Mode Port Configuration Port Configuration Register The Port Configuration (PCON) register (Figure 31) configures the comparator output on Port 3. It is located in the expanded register 2 at Bank F, location 00. PCON(FH)00h D7 D6 D5 D4 D3 D2 D1 D0 Comparator Output Port 3 0 P34, P37 Standard Output* 1 P34, P37 Comparator Output Port 1 0: Open-Drain 1: Push-Pull* Port 0 0: Open-Drain 1: Push-Pull* Reserved (Must be 1) * Default setting after reset Figure 31. Port Configuration Register (PCON) (Write Only) Comparator Output Port 3 (D0) Bit 0 controls the comparator used in Port 3. A 1 in this location brings the comparator outputs to P34 and P37, and a 0 releases the Port to its standard I/O configuration. PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 53 Port 1 Output Mode (D1) Bit 1 controls the output mode of port 1. A 1 in this location sets the output to push-pull, and a 0 sets the output to open-drain. Port 0 Output Mode (D2) Bit 2 controls the output mode of port 0. A 1 in this location sets the output to push-pull, and a 0 sets the output to open-drain. Stop-Mode Recovery Stop-Mode Recovery Register (SMR) This register selects the clock divide value and determines the mode of STOP mode Recovery (Figure 32). All bits are write only except bit 7, which is read only. Bit 7 is a flag bit that is hardware set on the condition of Stop recovery and reset by a power-on cycle. Bit 6 controls whether a low level or a high level at the XORgate input (Figure 34) is required from the recovery source. Bit 5 controls the reset delay after recovery. Bits D2, D3, and D4 of the SMR register specify the source of the Stop-Mode Recovery signal. Bits D0 determines if SCLK/TCLK are divided by 16 or not. The SMR is located in Bank F of the Expanded Register Group at address 0BH. PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 54 SMR(0F)0Bh D7 D6 D5 D4 D3 D2 D1 D0 SCLK/TCLK Divide-by-16 0 OFF * * 1 ON Reserved (Must be 0) Stop-Mode Recovery Source 000 POR Only * 001 Reserved 010 P31 011 P32 100 P33 101 P27 110 P2 NOR 0-3 111 P2 NOR 0-7 Stop Delay 0 OFF 1 ON * * * * Stop Recovery Level * * * 0 Low * 1 High Stop Flag 0 POR * 1 Stop Recovery * * * Default setting after reset * * Default setting after reset and stop-mode recovery * * * At the XOR gate input * * * * Default setting after reset. Recommended to be set to 1 if using a crystal or resonator clock source. Figure 32. STOP Mode Recovery Register SCLK/TCLK Divide-by-16 Select (D0) D0 of the SMR controls a divide-by-16 prescaler of SCLK/TCLK (Figure 33). This control selectively reduces device power consumption during normal processor execution (SCLK control) and/or Halt Mode (where TCLK sources interrupt logic). After STOP mode Recovery, this bit is set to a 0. PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 55 OSC /2 / 16 SMR, D0 Figure 33. SCLK Circuit SCLK TCLK Stop-Mode Recovery Source (D2, D3, and D4) These three bits of the SMR specify the wake-up source of the Stop recovery (Figure 34 and Table 19). Stop-Mode Recovery Register 2--SMR2(F)0Dh Table 18 lists and briefly describes the fields for this register. Table 18. SMR2(F)0Dh:STOP mode Recovery Register 2* Field Reserved Recovery Level Reserved Source Bit Position 7-------6-------5-------432-W W Value 0 0 1 0 000 001 010 011 100 101 110 111 00 Description Reserved (Must be 0) Low High Reserved (Must be 0) A. POR Only B. NAND of P23-P20 C. NAND of P27-P20 D. NOR of P33-P31 E. NAND of P33-P31 F. NOR of P33-P31, P00, P07 G. NAND of P33-P31, P00, P07 H. NAND of P33-P31, P22-P20 Reserved (Must be 0) Reserved Notes: ------10 * Port pins configured as outputs are ignored as an SMR recovery source. Indicates the value upon Power-On Reset PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 56 SMR D4 D3 D2 0 00 VCC SMR D4 D3 D2 0 10 P31 P23 SMR D4 D3 D2 0 11 P32 P27 SMR D4 D3 D2 1 00 P33 P20 VCC SMR2 D4 D3 D2 0 00 SMR2 D4 D3 D2 0 01 P20 SMR2 D4 D3 D2 0 10 P31 P32 P33 SMR2 D4 D3 D2 0 11 SMR D4 D3 D2 1 01 P27 SMR D4 D3 D2 110 P31 P32 P33 P31 P32 P33 P00 P07 P31 P32 P33 P00 P07 P31 P32 P33 P20 P21 SMR2 D4 D3 D2 1 00 P20 P23 P20 P27 SMR2 D4 D3 D2 1 01 SMR D4 D3 D2 1 11 SMR2 D4 D3 D2 110 SMR D6 SMR2 D4 D3 D2 1 11 To RESET and WDT Circuitry (Active Low) Figure 34. STOP Mode Recovery Source SMR2 D6 PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 57 Table 19. STOP Mode Recovery Source SMR:432 D4 0 0 0 0 1 1 1 1 D3 0 0 1 1 0 0 1 1 D2 0 1 0 1 0 1 0 1 Operation Description of Action POR and/or external reset recovery Reserved P31 transition P32 transition P33 transition P27 transition Logical NOR of P20 through P23 Logical NOR of P20 through P27 Note: Any Port 2 bit defined as an output drives the corresponding input to the default state. This condition allows the remaining inputs to control the AND/OR function. Refer to SMR2 register on page 58 for other recover sources. STOP Mode Recovery Delay Select (D5) This bit, if low, disables the TPOR delay after STOP mode recovery. The default configuration of this bit is 1. If the "fast" wake up is selected, the Stop-Mode Recovery source must be kept active for at least 10 TpC. Note: This bit must be set to 1 if using a crystal or resonator clock source. The TPOR delay allows the clock source to stabilize before executing instructions. STOP Mode Recovery Edge Select (D6) A 1 in this bit position indicates that a High level on any one of the recovery sources wakes the CrimzonTM ZLR32300 from STOP mode. A 0 indicates Low level recovery. The default is 0 on POR. Cold or Warm Start (D7) This bit is read only. It is set to 1 when the device is recovered from STOP mode. The bit is set to 0 when the device reset is other than STOP Mode Recovery (SMR). PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 58 STOP Mode Recovery Register 2 (SMR2) This register determines the mode of STOP Mode Recovery for SMR2 (Figure 35). SMR2(0F)Dh D7 D6 D5 D4 D3 D2 D1 D0 Reserved (Must be 0) Reserved (Must be 0) Stop-Mode Recovery Source 2 000 POR Only * 001 NAND P20, P21, P22, P23 010 NAND P20, P21, P22, P23, P24, P25, P26, P27 011 NOR P31, P32, P33 100 NAND P31, P32, P33 101 NOR P31, P32, P33, P00, P07 110 NAND P31, P32, P33, P00, P07 111 NAND P31, P32, P33, P20, P21, P22 Reserved (Must be 0) Recovery Level * * 0 Low * 1 High Reserved (Must be 0) Note: If used in conjunction with SMR, either of the two specified events causes a Stop-Mode Recovery. * Default setting after reset * * At the XOR gate input Figure 35. STOP Mode Recovery Register 2 ((0F)DH:D2-D4, D6 Write Only) If SMR2 is used in conjunction with SMR, either of the specified events causes a STOP mode Recovery. Note: Port pins configured as outputs are ignored as an SMR or SMR2 recovery source. For example, if the NAND or P23-P20 is selected as the recovery source and P20 is configured as an output, the remaining SMR pins (P23-P21) form the NAND equation. PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 59 Watch-Dog Timer Mode Watch-Dog Timer Mode Register (WDTMR) The Watch-Dog Timer (WDT) is a retriggerable one-shot timer that resets the Z8(R) if it reaches its terminal count. The WDT must initially be enabled by executing the WDT instruction. On subsequent executions of the WDT instruction, the WDT is refreshed. The WDT circuit is driven by an on-board RC-oscillator. The WDT instruction affects the Zero (Z), Sign (S), and Overflow (V) flags. The POR clock source the internal RC-oscillator. Bits 0 and 1 of the WDT register control a tap circuit that determines the minimum timeout period. Bit 2 determines whether the WDT is active during HALT, and Bit 3 determines WDT activity during Stop. Bits 4 through 7 are reserved (Figure 36). This register is accessible only during the first 60 processor cycles (120 XTAL clocks) from the execution of the first instruction after Power-On-Reset, Watch-Dog Reset, or a Stop-Mode Recovery (Figure 35). After this point, the register cannot be modified by any means (intentional or otherwise). The WDTMR cannot be read. The register is located in Bank F of the Expanded Register Group at address location 0Fh. It is organized as shown in Figure 36. WDTMR(0F)0Fh D7 D6 D5 D4 D3 D2 D1 D0 WDT TAP INT RC OSC 00 10 ms min. 01* 20 ms min. 10 40 ms min. 11 160 ms min. WDT During HALT 0 OFF 1 ON * WDT During Stop 0 OFF 1 ON * Reserved (Must be 0) * Default setting after reset Figure 36. WATCH-DOG TIMER Mode Register (Write Only) PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 60 WDT Time Select (D0, D1) This bit selects the WDT time period. It is configured as indicated in Table 20. Table 20. Watch-Dog Timer Time Select D1 0 0 1 1 D0 0 1 0 1 Timeout of Internal RC-Oscillator 10ms min. 20ms min. 40ms min. 160ms min. WDTMR During Halt (D2) This bit determines whether or not the WDT is active during HALT Mode. A 1 indicates active during HALT. The default is 1. See Figure 37. PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 61 5 Clock Filter *CLR2 CLK 18 Clock RESET RESET Generator Internal RESET Active High WDT TAP SELECT XTAL Internal RC Oscillator. Low Operating Voltage Det. POR 10 ms 20 ms 40 ms 160 CLK WDT/POR Counter Chain *CLR1 VDD VBO WDT From STOP mode Recovery Stop Delay Select (SMR) + - VDD 12-ns Glitch Filter * CLR1 and CLR2 enable the WDT/POR and 18 Clock Reset timers respectively upon a Low-to-High input translation. Figure 37. Resets and WDT WDTMR During STOP (D3) This bit determines whether or not the WDT is active during STOP Mode. A 1 indicates active during Stop. The default is 1. ROM Selectable Options There are seven ROM Selectable Options to choose from based on ROM code requirements. These are listed in Table 21. PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 62 Table 21. ROM Selectable Options Port 00-03 Pull-Ups Port 04-07 Pull-Ups Port 10-13 Pull-Ups Port 14-17 Pull-Ups Port 20-27 Pull-Ups Port 3 Pull-Ups On/Off On/Off On/Off On/Off On/Off On/Off Watch-Dog Timer at Power-On Reset On/Off Voltage Brown-Out/Standby An on-chip Voltage Comparator checks that the VDD is at the required level for correct operation of the device. Reset is globally driven when VDD falls below VBO. A small drop in VDD causes the XTAL1 and XTAL2 circuitry to stop the crystal or resonator clock. If the VDD is allowed to stay above VRAM, the RAM content is preserved. When the power level is returned to above VBO, the device performs a POR and functions normally. Low-Voltage Detection Low-Voltage Detection Register--LVD(D)0CH Note: Voltage detection does not work at STOP mode. It must be disabled during STOP mode in order to reduce current. Field LVD Bit Position 76543-------2-------1-------0 R R R/W 1 0* 1 0* 1 0* Description Reserved No Effect HVD flag set HVD flag reset LVD flag set LVD flag reset Enable VD Disable VD *Default after POR PS022607-1205 Functional Description CrimzonTM ZLR32300 Product Specification 63 Note: Do not modify register P01M while checking a low-voltage condition. Switching noise of both ports 0 and 1 together might trigger the LVD flag. Voltage Detection and Flags The Voltage Detection register (LVD, register 0Ch at the expanded register bank 0Dh) offers an option of monitoring the VCC voltage. The Voltage Detection is enabled when bit 0 of LVD register is set. Once Voltage Detection is enabled, the the VCC level is monitored in real time. The flags in the LVD register valid 20uS after Voltage Detection is enabled. The HVD flag (bit 2 of the LVD register) is set only if VCC is higher than VHVD. The LVD flag (bit 1 of the LVD register) is set only if VCC is lower than the VLVD. When Voltage Detection is enabled, the LVD flag also triggers IRQ5. The IRQ bit 5 latches the low voltage condition until it is cleared by instructions or reset. The IRQ5 interrupt is served if it is enabled in the IMR register. Otherwise, bit 5 of IRQ register is latched as a flag only. Note: If it is necessary to receive an LVD interrupt upon power-up at an operating voltage lower than the low battery detect threshold, enable interrupts using the Enable Interrupt instruction (EI) prior to enabling the voltage detection. Expanded Register File Control Registers (0D) The expanded register file control registers (0D) are depicted in Figures 38 through Figure 42. PS022607-1205 Expanded Register File Control Registers (0D) CrimzonTM ZLR32300 Product Specification 64 CTR0(0D)00h D7 D6 D5 D4 D3 D2 D1 D0 0 P34 as Port Output * 1 Timer8 Output 0 Disable T8 Timeout Interrupt** 1 Enable T8 Timeout Interrupt 0 Disable T8 Data Capture Interrupt** 1 Enable T8 Data Capture Interrupt 00 01 10 11 R R W W SCLK on T8** SCLK/2 on T8 SCLK/4 on T8 SCLK/8 on T8 0 No T8 Counter Timeout** 1 T8 Counter Timeout Occurred 0 No Effect 1 Reset Flag to 0 0 Modulo-N* 1 Single Pass R R W W 0 T8 Disabled * 1 T8 Enabled 0 Stop T8 1 Enable T8 * Default setting after reset **Default setting after reset. Not reset with a Stop Mode recovery. Figure 38. TC8 Control Register ((0D)O0H: Read/Write Except Where Noted) PS022607-1205 Expanded Register File Control Registers (0D) CrimzonTM ZLR32300 Product Specification 65 CTR1(0D)01h D7 D6 D5 D4 D3 D2 D1 D0 Transmit Mode* R/W 0 T16_OUT is 0 initially* 1 T16_OUT is 1 initially Demodulation Mode R 0 No Falling Edge Detection R 1 Falling Edge Detection W 0 No Effect W 1 Reset Flag to 0 Transmit Mode* R/W 0 T8_OUT is 0 initially* 1 T8_OUT is 1 initially Demodulation Mode R 0 No Rising Edge Detection R 1 Rising Edge Detection W 0 No Effect W 1 Reset Flag to 0 Transmit Mode* 0 0 Normal Operation* 0 1 Ping-Pong Mode 1 0 T16_OUT = 0 1 1 T16_OUT = 1 Demodulation Mode 0 0 No Filter 0 1 4 SCLK Cycle Filter 1 0 8 SCLK Cycle Filter 1 1 Reserved Transmit Mode/T8/T16 Logic 0 0 AND** 0 1 OR 1 0 NOR 1 1 NAND Demodulation Mode 0 0 Falling Edge Detection 0 1 Rising Edge Detection 1 0 Both Edge Detection 1 1 Reserved Transmit Mode 0 P36 as Port Output * 1 P36 as T8/T16_OUT Demodulation Mode 0 P31 as Demodulator Input 1 P20 as Demodulator Input * Default setting after reset. **Default setting after reset. Not reset with a Stop Mode recovery. Transmit/Demodulation Mode 0 Transmit Mode * 1 Demodulation Mode Figure 39. T8 and T16 Common Control Functions ((0D)01H: Read/Write) PS022607-1205 Expanded Register File Control Registers (0D) CrimzonTM ZLR32300 Product Specification 66 Notes: Take care in differentiating the TRANSMIT Mode from DEMODULATION Mode. Depending on which of these two modes is operating, the CTR1 bit has different functions. Changing from one mode to another cannot be performed without disabling the counter/timers. CTR2(0D)02h D7 D6 D5 D4 D3 D2 D1 D0 0 P35 is Port Output * 1 P35 is TC16 Output 0 Disable T16 Timeout Interrupt* 1 Enable T16 Timeout Interrupt 0 Disable T16 Data Capture Interrupt** 1 Enable T16 Data Capture Interrupt 0 0 1 1 R R W W 0 1 0 1 0 1 0 1 SCLK on T16** SCLK/2 on T16 SCLK/4 on T16 SCLK/8 on T16 No T16 Timeout** T16 Timeout Occurs No Effect Reset Flag to 0 Transmit Mode 0 Modulo-N for T16* 0 Single Pass for T16 Demodulator Mode 0 T16 Recognizes Edge 1 T16 Does Not Recognize Edge R R W W 0 1 0 1 T16 Disabled * T16 Enabled Stop T16 Enable T16 * Default setting after reset. **Default setting after reset. Not reset with a Stop Mode recovery. Figure 40. T16 Control Register ((0D) 2H: Read/Write Except Where Noted) PS022607-1205 Expanded Register File Control Registers (0D) CrimzonTM ZLR32300 Product Specification 67 CTR3(0D)03h D7 D6 D5 D4 D3 D2 D1 D0 Reserved 0 No Effect 1 Always reads 11111 Sync Mode 0** Disable Sync Mode 1 Enable Sync Mode T8 Enable 0* Counter Disabled 1 Counter Enabled 0 Stop Counter 1 Enable Counter T16 Enable 0* Counter Disabled 1 Counter Enabled 0 Stop Counter 1 Enable Counter * Default setting after reset. **Default setting after reset. Not reset with a Stop Mode recovery. Figure 41. T8/T16 Control Register (0D)03H: Read/Write (Except Where Noted) Note: If Sync Mode is enabled, the first pulse of T8 (carrier) is always synchronized with T16 (demodulated signal). It can always provide a full carrier pulse. PS022607-1205 Expanded Register File Control Registers (0D) CrimzonTM ZLR32300 Product Specification 68 LVD(0D)0Ch D7 D6 D5 D4 D3 D2 D1 D0 Voltage Detection 0: Disable * 1: Enable LVD Flag (Read only) 0: LVD flag reset * 1: LVD flag set HVD Flag (Read only) 0: HVD flag reset * 1: HVD flag set Reserved (Must be 0) * Default setting after reset. Figure 42. Voltage Detection Register Note: Do not modify register P01M while checking a low-voltage condition. Switching noise of both ports 0 and 1 together might trigger the LVD flag. Expanded Register File Control Registers (0F) The expanded register file control registers (0F) are depicted in Figures 43 through Figure 56. PS022607-1205 Expanded Register File Control Registers (0F) CrimzonTM ZLR32300 Product Specification 69 PCON(0F)00h D7 D6 D5 D4 D3 D2 D1 D0 Comparator Output Port 3 0 P34, P37 Standard Output * 1 P34, P37 Comparator Output Port 1 0: Open-Drain 1: Push-Pull* Port 0 0: Open-Drain 1: Push-Pull * Reserved (Must be 1) * Default setting after reset Figure 43. Port Configuration Register (PCON)(0F)00H: Write Only) PS022607-1205 Expanded Register File Control Registers (0F) CrimzonTM ZLR32300 Product Specification 70 SMR(0F)0Bh D7 D6 D5 D4 D3 D2 D1 D0 SCLK/TCLK Divide-by-16 0 OFF * 1 ON Reserved (Must be 0) Stop-Mode Recovery Source 000 POR Only * * 001 Reserved 010 P31 011 P32 100 P33 101 P27 110 P2 NOR 0-3 111 P2 NOR 0-7 Stop Delay 0 OFF 1 ON * * * * Stop Recovery Level * * * 0 Low ** 1 High Stop Flag 0 POR * * * * * 1 Stop Recovery * * * Default setting after reset * * Default setting after reset and stop-mode recovery * * * At the XOR gate input * * * * Default setting after reset. Recommended to be set to 1 if using a crystal or resonator clock source.Not reset with Stop Mode recovery. * * * * * Default setting after Power-On Reset. Figure 44. STOP mode Recovery Register ((0F)0BH: D6-D0=Write Only, D7=Read Only) PS022607-1205 Expanded Register File Control Registers (0F) CrimzonTM ZLR32300 Product Specification 71 SMR2(0F)0Dh D7 D6 D5 D4 D3 D2 D1 D0 Reserved (Must be 0) Reserved (Must be 0) Stop-Mode Recovery Source 2 000 POR Only * 001 NAND P20, P21, P22, P23 010 NAND P20, P21, P22, P23, P24, P25, P26, P27 011 NOR P31, P32, P33 100 NAND P31, P32, P33 101 NOR P31, P32, P33, P00, P07 110 NAND P31, P32, P33, P00, P07 111 NAND P31, P32, P33, P20, P21, P22 Reserved (Must be 0) Recovery Level * * 0 Low 1 High Reserved (Must be 0) Note: If used in conjunction with SMR, either of the two specified events causes a Stop-Mode Recovery. * Default setting after reset. Not reset with a Stop Mode recovery. * * At the XOR gate input Figure 45. STOP mode Recovery Register 2 ((0F)0DH:D2-D4, D6 Write Only) PS022607-1205 Expanded Register File Control Registers (0F) CrimzonTM ZLR32300 Product Specification 72 WDTMR(0F)0Fh D7 D6 D5 D4 D3 D2 D1 D0 WDT TAP INT RC OSC 00 10 ms min. 01* 20 ms min. 10 40 ms min. 11 160 ms min. WDT During HALT 0 OFF 1 ON * WDT During Stop 0 OFF 1 ON * Reserved (Must be 0) * Default setting after reset. Not reset wit a Stop Mode recovery. Figure 46. Watch-Dog Timer Register ((0F) 0FH: Write Only) Standard Control Registers R246P2M(F6H) D7 D6 D5 D4 D3 D2 D1 D0 P27-P20 I/O Definition 0 Defines bit as OUTPUT 1 Defines bit as INPUT * * Default setting after reset. Not reset wit a Stop Mode recovery. Figure 47. Port 2 Mode Register (F6H: Write Only) PS022607-1205 Standard Control Registers CrimzonTM ZLR32300 Product Specification 73 R247P3M(F7H) D7 D6 D5 D4 D3 D2 D1 D0 0: Port 2 Open Drain * 1: Port 2 Push-Pull 0= P31, P32 Digital Mode* 1= P31, P32 Analog Mode Reserved (Must be 0) * Default setting after reset. Not reset wit a Stop Mode recovery. Figure 48. Port 3 Mode Register (F7H: Write Only) PS022607-1205 Standard Control Registers CrimzonTM ZLR32300 Product Specification 74 R248 P01M(F8H) D7 D6 D5 D4 D3 D2 D1 D0 P00-P03 Mode 0: Output 1: Input * Reserved (Must be 0) Reserved (Must be 1) P17-P10 Mode 0: Byte Output 1: Byte Input* Reserved (Must be 0) P07-P04 Mode 0: Output 1: Input * Reserved (Must be 0) * Default setting after reset; only P00, P01 and P07 are available on CrimzonTM ZLR32300 20-pin configurations. Figure 49. Port 0 and 1 Mode Register (F8H: Write Only) PS022607-1205 Standard Control Registers CrimzonTM ZLR32300 Product Specification 75 R249 IPR(F9H) D7 D6 D5 D4 D3 D2 D1 D0 Interrupt Group Priority 000 Reserved 001 C > A > B 010 A > B >C 011 A > C > B 100 B > C > A 101 C > B > A 110 B > A > C 111 Reserved IRQ1, IRQ4, Priority (Group C) 0: IRQ1 > IRQ4 1: IRQ4 > IRQ1 IRQ0, IRQ2, Priority (Group B) 0: IRQ2 > IRQ0 1: IRQ0 > IRQ2 IRQ3, IRQ5, Priority (Group A) 0: IRQ5 > IRQ3 1: IRQ3 > IRQ5 Reserved; must be 0 Figure 50. Interrupt Priority Register (F9H: Write Only) PS022607-1205 Standard Control Registers CrimzonTM ZLR32300 Product Specification 76 R250 IRQ(FAH) D7 D6 D5 D4 D3 D2 D1 D0 IRQ0 = P32 Input IRQ1 = P33 Input IRQ2 = P31 Input IRQ3 = T16 IRQ4 = T8 IRQ5 = LVD Inter Edge P31 P32 = 00 P31 P32 = 01 P31 P32 = 10 P31 P32 = 11 Figure 51. Interrupt Request Register (FAH: Read/Write) R251 IMR(FBH) D7 D6 D5 D4 D3 D2 D1 D0 1 Enables IRQ5-IRQ0 (D0 = IRQ0) Reserved (Must be 0) 0 Master Interrupt Disable * 1 Master Interrupt Enable * * * Default setting after reset * * Only by using EI, DI instruction; DI is required before changing the IMR register Figure 52. Interrupt Mask Register (FBH: Read/Write) PS022607-1205 Standard Control Registers CrimzonTM ZLR32300 Product Specification 77 R252 Flags(FCH) D7 D6 D5 D4 D3 D2 D1 D0 User Flag F1 User Flag F2 Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Tag Zero Flag Carry Flag Figure 53. Flag Register (FCH: Read/Write) R253 RP(FDH) D7 D6 D5 D4 D3 D2 D1 D0 Expanded Register Bank Pointer Working Register Pointer Default setting after reset = 0000 0000 Figure 54. Register Pointer (FDH: Read/Write) PS022607-1205 Standard Control Registers CrimzonTM ZLR32300 Product Specification 78 R254 SPH(FEH) D7 D6 D5 D4 D3 D2 D1 D0 General-Purpose Register Figure 55. Stack Pointer High (FEH: Read/Write) R255 SPL(FFH) D7 D6 D5 D4 D3 D2 D1 D0 Stack Pointer Low Byte (SP7-SP0) Figure 56. Stack Pointer Low (FFH: Read/Write) Package Information Package information for all versions of CrimzonTM ZLR32300 is depicted in Figures 57 through Figure 63. PS022607-1205 Package Information CrimzonTM ZLR32300 Product Specification 79 Figure 57. 20-Pin PDIP Package Diagram Figure 58. 20-Pin SOIC Package Diagram PS022607-1205 Package Information CrimzonTM ZLR32300 Product Specification 80 Figure 59. 20-Pin SSOP Package Diagram PS022607-1205 Package Information CrimzonTM ZLR32300 Product Specification 81 Figure 60. 28-Pin SOIC Package Diagram PS022607-1205 Package Information CrimzonTM ZLR32300 Product Specification 82 Figure 61. 28-Pin PDIP Package Diagram PS022607-1205 Package Information CrimzonTM ZLR32300 Product Specification 83 D 28 15 C SYMBOL A E H A1 A2 B C 1 14 DETAIL A D E e Q1 H L A2 7.65 0.63 MIN 1.73 0.05 1.68 0.25 0.09 10.07 5.20 10.20 5.30 0.65 TYP 7.80 0.75 7.90 0.95 0.301 0.025 MILLIMETER NOM 1.86 0.13 1.73 MAX 1.99 0.21 1.78 0.38 0.20 10.33 5.38 MIN 0.068 0.002 0.066 0.010 0.004 0.397 0.205 0.006 0.402 0.209 0.0256 TYP 0.307 0.030 0.311 0.037 INCH NOM 0.073 0.005 0.068 MAX 0.078 0.008 0.070 0.015 0.008 0.407 0.212 A1 A e B SEATING PLANE CONTROLLING DIMENSIONS: MM LEADS ARE COPLANAR WITHIN .004 INCHES. L 0-8 DETAIL 'A' Figure 62. 28-Pin SSOP Package Diagram PS022607-1205 Package Information CrimzonTM ZLR32300 Product Specification 84 D 48 25 c E H 1 24 Detail A A2 1 A CONTROLLING DIMENSIONS : MM LEADS ARE COPLANAR WITHIN .004 INCH SEATING PLANE e b L 0-8 Detail A Figure 63. 48-Pin SSOP Package Design Note: Please check with ZiLOG on the actual bonding diagram and coordinate for chip-on-board assembly. PS022607-1205 Package Information CrimzonTM ZLR32300 Product Specification 85 Ordering Information I Memory Size 32K Part Number Description ZLR32300H4832G ZLR32300H2832G ZLR32300P2832G ZLR32300S2832G ZLR32300H2032G ZLR32300P2032G ZLR32300S2032G 24K ZLR32300H4824G ZLR32300H2824G ZLR32300P2824G ZLR32300S2824G ZLR32300H2024G ZLR32300P2024G ZLR32300S2024G 16K ZLR32300H4816G 8K ZLR32300H4808G 4K ZLR32300H4804G 48-pin SSOP 32K ROM 28-pin SSOP 32K ROM 28-pin PDIP 32K ROM 28-pin SOIC 32K ROM 20-pin SSOP 32K ROM 20-pin PDIP 32K ROM 20-pin SOIC 32K ROM 48-pin SSOP 24K ROM 28-pin SSOP 24K ROM 28-pin PDIP 24K ROM 28-pin SOIC 24K ROM 20-pin SSOP 24K ROM 20-pin PDIP 24K ROM 20-pin SOIC 24K ROM 48-pin SSOP 16K ROM 48-pin SSOP 8K ROM 48-pin SSOP 4K ROM ZLP128ICE01ZEM ZLP323ICE01ZAC Note: Contact www.zilog.com for the die form. In-Circuit Emulator 40-PDIP/48-SSOP Accessory Kit PS022607-1205 Ordering Information CrimzonTM ZLR32300 Product Specification 86 For fast results, contact your local ZiLOG sales office for assistance in ordering the part desired. Part Number Description ZiLOG part numbers consist of a number of components, as shown in Figure 64. The example part number ZLR32300H2832G is a CrimzonTM masked ROM product in a 28-pin SSOP package, with 32 KB of ROM and built with lead-free solder. Z LR 32300 H 28 32 G Environmental Flow: G = Lead Free Memory Size: 32 = 32KB 24 = 24KB 16 = 16KB 8 = 8KB 4 = 4KB Number of Pins in Package: 48 = 48 Pins 40 = 40 Pins 28 = 28 Pins 20 = 20 Pins Package Type: H = SSOP P = PDIP S = SOIC Product Number: 32300 Product Line: CrimzonTM ROM ZiLOG Product Prefix Figure 64. Part Number Description Example PS022607-1205 Part Number Description CrimzonTM ZLR32300 Product Specification 87 Index Numerics 16-bit counter/timer circuits 43 20-pin DIP package diagram 79 20-pin SSOP package diagram 80 28-pin DIP package diagram 82 28-pin SOICpackage diagram 81 28-pin SSOP package diagram 83 40-pin DIP package diagram 83 48-pin SSOP package diagram 84 8-bit counter/timer circuits 39 counter/timer 16-bit circuits 43 8-bit circuits 39 brown-out voltage/standby 61 clock 50 demodulation mode count capture flowchart 41 demodulation mode flowchart 42 diagram 3 EPROM selectable options 61 glitch filter circuitry 37 halt instruction 51 input circuit 37 interrupt block diagram 48 interrupt types, sources and vectors 49 oscillator configuration 50 output circuit 46 ping-pong mode 45 port configuration register 52 resets and WDT 61 SCLK circuit 55 stop instruction 51 stop mode recovery register 54 stop mode recovery register 2 58 stop mode recovery source 56 T16 demodulation mode 44 T16 transmit mode 43 T16_OUT in modulo-N mode 44 T16_OUT in single-pass mode 44 T8 demodulation mode 40 T8 transmit mode 37 T8_OUT in modulo-N mode 40 T8_OUT in single-pass mode 40 transmit mode flowchart 38 voltage detection and flags 62 watch-dog timer mode register 59 watch-dog timer time select 60 CTR(D)01h T8 and T16 Common Functions 32 A absolute maximum ratings 10 AC characteristics 13 timing diagram 13 address spaces, basic 2 architecture 2 expanded register file 25 B basic address spaces 2 block diagram, ZLP32300 functional 4 C capacitance 11 characteristics AC 13 DC 11 clock 50 comparator inputs/outputs 22 configuration port 0 16 port 1 17 port 2 18 port 3 19 port 3 counter/timer 21 PS022607-1205 Index CrimzonTM ZLR32300 Product Specification 88 D DC characteristics 11 demodulation mode count capture flowchart 41 flowchart 42 T16 44 T8 40 description functional 22 general 2 pin 4 E EPROM selectable options 61 expanded register file 23 expanded register file architecture 25 expanded register file control registers 68 flag 77 interrupt mask register 76 interrupt priority register 75 interrupt request register 76 port 0 and 1 mode register 74 port 2 configuration register 72 port 3 mode register 73 port configuration register 72 register pointer 77 stack pointer high register 78 stack pointer low register 78 stop-mode recovery register 70 stop-mode recovery register 2 71 T16 control register 66 T8 and T16 common control functions register 64 T8/T16 control register 67 TC8 control register 62 watch-dog timer register 72 ZLP32300 1 functional description counter/timer functional blocks 37 CTR(D)01h register 32 CTR0(D)00h register 30 CTR2(D)02h register 34 CTR3(D)03h register 36 expanded register file 23 expanded register file architecture 25 HI16(D)09h register 29 HI8(D)0Bh register 29 L08(D)0Ah register 29 L0I6(D)08h register 29 program memory map 23 RAM 22 register description 62 register file 27 register pointer 26 register pointer detail 28 SMR2(F)0D1h register 37 stack 28 TC16H(D)07h register 29 TC16L(D)06h register 30 TC8H(D)05h register 30 TC8L(D)04h register 30 G glitch filter circuitry 37 H halt instruction, counter/timer 51 I input circuit 37 interrupt block diagram, counter/timer 48 interrupt types, sources and vectors 49 F features standby modes 1 L low-voltage detection register 62 PS022607-1205 Index CrimzonTM ZLR32300 Product Specification 89 M memory, program 22 modulo-N mode T16_OUT 44 T8_OUT 40 O oscillator configuration 50 output circuit, counter/timer 46 P package information 20-pin DIP package diagram 79 20-pin SSOP package diagram 80 28-pin DIP package diagram 82 28-pin SOIC package diagram 81 28-pin SSOP package diagram 83 40-pin DIP package diagram 83 48-pin SSOP package diagram 84 pin configuration 20-pin DIP/SOIC/SSOP 5 28-pin DIP/SOIC/SSOP 6 40- and 48-pin 8 40-pin DIP 7 48-pin SSOP 8 pin functions port 0 (P07 - P00) 15 port 0 (P17 - P10) 16 port 0 configuration 16 port 1 configuration 17 port 2 (P27 - P20) 17 port 2 (P37 - P30) 18 port 2 configuration 18 port 3 configuration 19 port 3 counter/timer configuration 21 reset) 22 XTAL1 (time-based input 15 XTAL2 (time-based output) 15 ping-pong mode 45 port 0 configuration 16 port 0 pin function 15 port 1 configuration 17 port 1 pin function 16 port 2 configuration 18 port 2 pin function 17 port 3 configuration 19 port 3 pin function 18 port 3counter/timer configuration 21 port configuration register 52 power connections 3 power supply 5 precharacterization product 87 program memory 22 map 23 R ratings, absolute maximum 10 register 58 CTR(D)01h 32 CTR0(D)00h 30 CTR2(D)02h 34 CTR3(D)03h 36 flag 77 HI16(D)09h 29 HI8(D)0Bh 29 interrupt priority 75 interrupt request 76 interruptmask 76 L016(D)08h 29 L08(D)0Ah 29 LVD(D)0Ch 62 pointer 77 port 0 and 1 74 port 2 configuration 72 port 3 mode 73 port configuration 52, 72 SMR2(F)0Dh 37 stack pointer high 78 stack pointer low 78 stop mode recovery 54 stop mode recovery 2 58, 71 stop-mode recovery 70 T16 control 66 T8 and T16 common control functions 64 PS022607-1205 Index CrimzonTM ZLR32300 Product Specification 90 T8/T16 control 67 TC16H(D)07h 29 TC16L(D)06h 30 TC8 control 62 TC8H(D)05h 30 TC8L(D)04h 30 voltage detection 68 watch-dog timer 72 register description counter/timer2 ls-byte hold 30 counter/timer2 ms-byte hold 29 counter/timer8 control 30 counter/timer8 high hold 30 counter/timer8 low hold 30 CTR2 counter/timer 16 Control 34 CTR3 T8/T16 control 36 stop mode recovery2 37 T16_capture_LO 29 T8 and T16 common functions 32 T8_capture_HI 29 T8_capture_LO 29 register file 27 expanded 23 register pointer 26 detail 28 reset pin function 22 resets and WDT 61 T T16 transmit mode 43 T16_Capture_HI 29 T8 transmit mode 37 T8_Capture_HI 29 test conditions, standard 10 test load diagram 10 timing diagram, AC 13 transmit mode flowchart 38 V VCC 5 voltage brown-out/standby 61 detection and flags 62 voltage detection register 68 W watch-dog timer mode registerwatch-dog timer mode register 59 time select 60 X XTAL1 5 XTAL1 pin function 15 XTAL2 5 XTAL2 pin function 15 S SCLK circuit 55 single-pass mode T16_OUT 44 T8_OUT 40 stack 28 standard test conditions 10 standby modes 1 stop instruction, counter/timer 51 stop mode recovery 2 register 58 source 56 stop mode recovery 2 58 stop mode recovery register 54 Z ZLP32300 family members 1 PS022607-1205 Index |
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